A 2V, 2.3/4.6 GHz dual-band CMOS frequency synthesizer

Author

Wei-Zen Chen ; Jia-Xian Chang ; Ying-Jen Hong ; Meng-Tzer Wong ; Chien-Liang Kuo

Author_Institution

Dept. of Electr. Eng., Nat. Central Univ., Chung-li, Taiwan

fYear

2002

fDate

3-4 June 2002

Firstpage

169

Lastpage

172

Abstract

This paper describes the design of a CMOS frequency synthesizer for 2.3/4.6 GHz wireless applications. This synthesizer provides dual band output signals by means of a novel frequency doubling technique. Output frequency of the proposed synthesizer ranges from 1.87 GHz-2.3 GHz and 3.74 GHz-4.6 GHz. Fabricated in a 0.35 /spl mu/m CMOS process, this chip consumes a total power of 80 mW from a single 2 V supply. Chip size is 3210 /spl mu/m/spl times/2410 /spl mu/m.

Keywords

CMOS analogue integrated circuits; cellular radio; field effect MMIC; frequency synthesizers; low-power electronics; personal communication networks; phase locked loops; transceivers; 0.35 micron; 1.87 to 2.3 GHz; 2 V; 2.3 GHz; 3.74 to 4.6 GHz; 4.6 GHz; 80 mW; CMOS; RF front-end ICs; chip size; dual band output signals; dual-band frequency synthesizer; frequency doubling technique; portable communication devices; total power; wireless applications; wireless transceiver; Circuit optimization; Dual band; Energy consumption; Frequency conversion; Frequency synthesizers; Phase frequency detector; Radio frequency; Transceivers; Tuning; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Frequency Integrated Circuits (RFIC) Symposium, 2002 IEEE

Conference_Location

Seattle, WA, USA

ISSN

1529-2517

Print_ISBN

0-7803-7246-8

Type

conf

DOI

10.1109/RFIC.2002.1011948

Filename

1011948