DocumentCode :
1838079
Title :
A high-speed variable phase accumulator for an ADPLL architecture
Author :
Xu, Liangge ; Lindfors, Saska
Author_Institution :
Electron. Circuit Design Lab., Helsinki Univ. of Technol., Espoo
fYear :
2008
fDate :
18-21 May 2008
Firstpage :
1736
Lastpage :
1739
Abstract :
This paper presents a high-speed topology for the variable phase accumulator (VPA) in an all digital phase-locked loop (ADPLL) architecture. The topology increases the speed of the VPA, which is a digital block running at the highest frequency in the ADPLL. The high-speed feature of the topology is achieved by exploiting the fact that the VPA output is used in the reference frequency domain while the circuit needs to handle the RF signal from the ADPLL output. The new topology minimizes the timing critical path and reduces the logic in the highest frequency domain to a shift register. As demonstrated in a 65-nm CMOS process, it allows the VPA to have a speed increase of about 60% without penalty in power dissipation or silicon area.
Keywords :
CMOS digital integrated circuits; digital phase locked loops; network topology; RF signal; all digital phase-locked loop architecture; circuit topolgy; high-speed variable phase accumulator; power dissipation; reference frequency domain; shift register; silicon area; size 65 nm; timing critical path; Circuit synthesis; Circuit topology; Digital integrated circuits; Frequency domain analysis; Frequency synthesizers; Phase locked loops; Radio frequency; Radiofrequency integrated circuits; Silicon; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
978-1-4244-1683-7
Electronic_ISBN :
978-1-4244-1684-4
Type :
conf
DOI :
10.1109/ISCAS.2008.4541773
Filename :
4541773
Link To Document :
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