Title :
Design considerations in a BiCMOS dual-modulus prescaler
Author :
Dulger, F. ; Sanchez-Sinencio, E. ; Bellaouar, A.
Author_Institution :
Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
Abstract :
Design considerations in a dual modulus divide by 32/33 prescaler with a 0.6/spl mu/m BiCMOS process are presented. Care was taken to design the ECL-based circuits to operate with as low supply voltage and current consumption as possible. The phase noise contribution of the integrated bandgap bias network is demonstrated through simulations. The tradeoff between the power consumption and the phase noise is pointed out and some guidelines are provided to improve the noise performance. Measurements confirm the functionality of the prescaler with a 2.5V supply drawing around 2.3mA at 2.35 GHz with an input sensitivity between -24dBm and 12dBm. The circuit operates with a supply voltage down to 2.1V but with limited input sensitivity.
Keywords :
BiCMOS digital integrated circuits; digital phase locked loops; emitter-coupled logic; frequency synthesizers; low-power electronics; phase noise; prescalers; 0.6 micron; 2.1 to 2.5 V; 2.3 mA; 2.35 GHz; BiCMOS; ECL-based circuits; bandgap bias network; current consumption; dual-modulus prescaler; functionality; input sensitivity; noise performance; phase noise; phase noise contribution; power consumption; supply voltage; Bandwidth; BiCMOS integrated circuits; Energy consumption; Frequency synthesizers; Instruments; Local oscillators; Noise measurement; Phase locked loops; Phase noise; Wireless communication;
Conference_Titel :
Radio Frequency Integrated Circuits (RFIC) Symposium, 2002 IEEE
Conference_Location :
Seattle, WA, USA
Print_ISBN :
0-7803-7246-8
DOI :
10.1109/RFIC.2002.1011950
