Inter-signal timing skew compensation of parallel links with voltage-mode incremental signaling

Inter-signal timing skew gives rise to reduced timing margins at the receiver and limits the data rate of parallel links. This paper proposes a new inter-signal timing skew compensation technique for parallel links with voltage-mode incremental signaling. The proposed technique employs an early/late block to detect the rising and falling edges of adjacent pulses generated at the output of comparators due to inter-signal timing skews, and subsequently to allocate the optimal sampling point of the samplers to maximize timing margins. Two delay-locked loops (DLLs) are employed to place the sampling clock to the optimal sampling position. The skew compensation range is quantified with reference of the delay range of the DLLs. The effectiveness of the proposed deskewing method is validated using a 1 Gbyte/s parallel link implemented in UMC-0.13 mum 1.2 V CMOS technology with three microstrip channels on a FR4 substrate.