Technical evaluation of a near chip scale size flip chip/plastic ball grid array package

Author

Jimarez, Miguel ; Li, Li ; Tytran, Cheryl ; Loveland, Cathy ; Obrzut, Jan

Author_Institution

Microelectronics, IBM Corp., Endicott, NY, USA

fYear

1998

fDate

25-28 May 1998

Firstpage

495

Lastpage

502

Abstract

Technical evaluation and reliability assessment have been performed for a near chip scale size package that utilizes microvias and the Flip Chip-Plastic Ball Grid Array technology. The microvias were photolithographically patterned in a build-up, Surface Laminar Circuit ^TM (SLC) interposer layers. The package accommodated a 12 mm×14 mm die with 700 controlled collapse chip connections (C4). The carrier dimensions were 21 mm×21 mm, 1.27 mm pitch with 255 EGA interconnections. The dimensions of the package, for which the target application was microprocessors, conformed to the JEDEC standards. It has been determined that this novel packaging construction is manufacturable and can satisfy the standard reliability requirements

Keywords

delamination; flip-chip devices; integrated circuit packaging; integrated circuit reliability; integrated circuit testing; microassembling; plastic packaging; 1.27 mm; 12 mm; 14 mm; 21 mm; C4 assembly; JEDEC standards; Surface Laminar Circuit interposer layers; ball grid array package; controlled collapse chip connections; microprocessor application; microvias; near CSP size flip chip/PBGA package; near chip scale size package; photolithographic patterning; plastic BGA package; reliability assessment; Chip scale packaging; Electronics packaging; Flip chip; Integrated circuit interconnections; Integrated circuit packaging; Laminates; Microprocessors; Plastic packaging; Stress; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Components & Technology Conference, 1998. 48th IEEE

Conference_Location

Seattle, WA

ISSN

0569-5503

Print_ISBN

0-7803-4526-6

Type

conf

DOI

10.1109/ECTC.1998.678739

Filename

678739