Title :
Integrated circuit implementation of a cortical neuron
Author :
Wijekoon, Jayawan H B ; Dudek, Piotr
Author_Institution :
Sch. of Electr. & Electron. Eng., Univ. of Manchester, Manchester
Abstract :
This paper presents an analogue integrated circuit implementation of a cortical neuron model. The VLSI chip prototype has been implemented in a 0.35 mum CMOS technology. The single neuron cell has a compact layout and very low energy consumption, in the range of 9 pJ per spike. Experimental results demonstrate the capability of the circuit to generate a realistic spike shape and a variety of spiking and bursting firing patterns. The models of various cortical neuron types are obtained in a single circuit, through the adjustment of two biasing voltages, making the circuit suitable for applications in reconfigurable neuromorphic devices that implement biologically plausible spiking neural networks.
Keywords :
CMOS analogue integrated circuits; VLSI; neural nets; CMOS technology; VLSI chip prototype; analogue integrated circuit implementation; biasing voltages; biologically plausible spiking neural networks; bursting firing patterns; cortical neuron model; reconfigurable neuromorphic devices; single neuron cell; spiking firing patterns; Analog integrated circuits; CMOS technology; Energy consumption; Integrated circuit modeling; Integrated circuit technology; Neurons; Prototypes; Semiconductor device modeling; Shape; Very large scale integration;
Conference_Titel :
Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
978-1-4244-1683-7
Electronic_ISBN :
978-1-4244-1684-4
DOI :
10.1109/ISCAS.2008.4541785
