Title :
Enhancement mode PHEMT low noise amplifier with LNA linearity control (IP3) and mitigated bypass switch
Author :
Kumar, S. ; Vice, M. ; Morkner, H. ; Wayne, L.
Author_Institution :
Agilent Technol., WSD R&D, Newark, CA, USA
Abstract :
A new LNA has been designed using single supply enhancement mode PHEMT process for WCDMA and other wireless application up to 6 GHz. The LNA has direct CMOS logic controllable integrated bypass-mitigated switch and LNA linearity (IP3) control switch. Two different kind of logic controls (0/3 V, 3/0 V) switch has been design for bypass-mitigated switch. In high linearity mode the LNA draws 8.5 mA current and has 15 dB gain, 1 dB noise figure, -6 dBm IP/sub 1dB,/, 7.3 dBm IIP3 with I/O return loss >11 dB. In low linearity mode the LNA draws 3.5 mA current and has 14 dB gain, 1.1 dB noise figure,, -6.5 dBm IP/sub 1dB,/, 2 dBm IIP3 with I/O return loss >11 dB. The LNA bypass-mitigated switch has <3.5 dB insertion loss and NF, I/O return loss >11 dB and draws negligible current with 3/0 V logic, /spl sim/200 /spl mu/A for 0/3 V logic. Due to well-behaved match of LNA in High Linearity/Low Linearity/Bypass modes, this LNA has minimum mismatch effect for duplexers; and filters in a receiver system.
Keywords :
HEMT integrated circuits; MMIC amplifiers; cellular radio; code division multiple access; field effect MMIC; impedance matching; integrated circuit noise; 1 dB; 1.1 dB; 14 dB; 15 dB; 200 muA; 3.5 mA; 8.5 mA; IIP3; WCDMA; direct CMOS logic controllable bypass-mitigated switch; duplexers; enhancement mode PHEMT low noise amplifier; high linearity mode; insertion loss; logic controls; low linearity mode; mismatch effect; receiver system; return loss; CMOS logic circuits; Gain; Insertion loss; Linearity; Logic design; Low-noise amplifiers; Multiaccess communication; Noise figure; PHEMTs; Switches;
Conference_Titel :
Radio Frequency Integrated Circuits (RFIC) Symposium, 2002 IEEE
Conference_Location :
Seattle, WA, USA
Print_ISBN :
0-7803-7246-8
DOI :
10.1109/RFIC.2002.1012034