Title :
Design of multiple-valued linear digital circuits for highly parallel unary operations
Author :
Nakajima, Masami ; Kameyama, Michitaka
Author_Institution :
Dept. of Comput. & Math. Sci., Tohoku Univ., Sendai, Japan
Abstract :
A design method for highly parallel multiple-valued linear digital circuits for unary operations using the concept of a cycle and a tree is proposed. In the circuit design, an analytical approach using a representation matrix is possible, so that the search procedure for optimal locally computable circuits becomes very simple. Some examples are shown to demonstrate the usefulness of the design algorithm
Keywords :
logic circuits; many-valued logics; parallel architectures; highly parallel; linear digital circuits; multiple-valued; representation matrix; search procedure; unary operations; Adders; Circuit synthesis; Combinational circuits; Concurrent computing; Design methodology; Digital circuits; Digital systems; Input variables; Integrated circuit interconnections; Very large scale integration;
Conference_Titel :
Multiple-Valued Logic, 1993., Proceedings of The Twenty-Third International Symposium on
Conference_Location :
Sacramento, CA
Print_ISBN :
0-8186-3350-6
DOI :
10.1109/ISMVL.1993.289546
