Title :
Motion estimation VLSI architecture for image coding
Author :
Privat, G. ; Renaudin, M.
Author_Institution :
CNET, Meylan, France
Abstract :
Special-purpose chips based on highly parallel architectures, for possible use in videophone, videoconference, digital TV distribution and HDTV codecs, are considered. Functional interface specifications for a motion estimator to be inserted in a coder system are detailed. The range of possible operative part-kernel architectures is derived, based on formal high-level synthesis methods. A novel implementation using redundant base 2 digital-serial arithmetic is presented, resulting in a compact (70000 transistors) motion estimation VLSI block
Keywords :
VLSI; digital arithmetic; digital signal processing chips; encoding; high definition television; parallel architectures; teleconferencing; videotelephony; HDTV codecs; VLSI architecture; digital TV distribution; formal high-level synthesis methods; highly parallel architectures; image coding; interface specifications; motion estimator; operative part-kernel architectures; redundant base 2 digital-serial arithmetic; videoconference; videophone; Codecs; Digital TV; Digital arithmetic; HDTV; High level synthesis; Image coding; Motion estimation; Parallel architectures; Very large scale integration; Videoconference;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1989. ICCD '89. Proceedings., 1989 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-1971-6
DOI :
10.1109/ICCD.1989.63332
