CMOS implementation and fabrication of the pseudo analog neuron

The pseudo-analog neuron (PAN) uses a transresistance amplifier and multivalued logic design techniques to implement the basic building blocks of artificial neural networks. The performance characteristics of PAN building blocks that were implemented in a standard 2-μm CMOS process are described. A two-layer network of PANs is used to implement various Boolean functions. The two-layer circuit computes ten weighted sum of inputs plus four thresholds in the first layer, and a four weighted sum plus one threshold in the second layer. All thresholding and weighted sums are propagated in 10 ns through both layers. This circuit dissipates 250 μW of average power, and occupies 288 μm×136 μm of silicon area