Integration of a mechanically reliable 65-nm node technology for low-k and ULK interconnects with various substrate and package types

Mechanical reliability is widely recognized as the primary obstacle to productionization of porous low-k materials. The combination of weak bulk and interfacial properties with increasingly complex geometries poses a considerable challenge at the 65-nm node. The final solution must be sufficiently robust so as to ensure compatibility with multiple substrate types, interconnect configurations and packages. In this work, material engineering, modeling, design rule tailoring, and assembly optimization are employed to achieve required assembly reliability for both wirebond and flip-chip packages, for both bulk and SOI substrates.