Title :
Full profile inter-layer dielectric CMP analysis
Author :
Chang, Runzi ; Spanos, Costas J.
Author_Institution :
Dept. of Electr. Eng., California Univ., Berkeley, CA, USA
Abstract :
Chemical mechanical polishing (CMP) is currently being used in the fabrication of state-of-the-art integrated circuits, and has been identified as an enabling technology for the semiconductor industry in its drive toward gigabit chips and sub-130 nm feature sizes. We present the application of a library-based specular spectroscopic scatterometry method, which is capable of getting a clear view of the profile evolution due to the oxide CMP process. This level of analysis will be crucial in building a rigorous CMP model in the near future
Keywords :
VLSI; chemical mechanical polishing; dielectric thin films; integrated circuit measurement; light scattering; semiconductor process modelling; 130 nm; CMP analysis; enabling technology; gigabit chips; inter-layer dielectric; library-based specular spectroscopic scatterometry method; oxide CMP process; profile evolution; Atomic force microscopy; Dielectrics; Fabrication; Metrology; Planarization; Radar measurements; Resists; Scanning electron microscopy; Semiconductor device modeling; Spectroscopy;
Conference_Titel :
Semiconductor Manufacturing Symposium, 2001 IEEE International
Conference_Location :
San Jose, CA
Print_ISBN :
0-7803-6731-6
DOI :
10.1109/ISSM.2001.962932
