Title :
Comprehensive process design for low-cost chip packaging with circuit-under-pad (CUP) structure in porous-SiOCH film
Author :
Tagami, M. ; Ohtake, H. ; Abe, M. ; Ito, F. ; Takeuchi, T. ; Ohto, K. ; Usami, T. ; Suzuki, M. ; Suzuki, T. ; Sashida, N. ; Hayashi, Y.
Author_Institution :
Syst. Devices Res. Labs., NEC Corp., Kanagawa, Japan
Abstract :
Chip packaging technology with a circuit-under-pad (CUP) structure is developed for porous SiOCH (k=2.55)/Cu dual-damascene interconnects. Wire bonding damage is mainly improved by the pad structure. For the molding process, it is important to decrease the coefficient of thermal expansion (CTE) of the molding compounds. Combining the stress controls in these packaging processes with the contrived low-k deposition, high performance 65 nm-node ULSI chips are furnished in low-cost QFP with conventional wire bonding.
Keywords :
ULSI; chip scale packaging; copper; dielectric thin films; integrated circuit interconnections; lead bonding; moulding; porous materials; silicon compounds; thermal expansion; 65 nm; SiOCH-Cu; ULSI; circuit-under-pad structure; coefficient of thermal expansion; dual-damascene interconnects; low-cost QFP; low-cost chip packaging; low-k deposition; molding compound CTE; packaging process stress control; porous dielectric films; quad-flat-package; wire bonding damage reduction; Acoustic testing; Adhesives; Bonding; Electronics packaging; Integrated circuit interconnections; Laboratories; National electric code; Process design; Stress; Wire;
Conference_Titel :
Interconnect Technology Conference, 2005. Proceedings of the IEEE 2005 International
Print_ISBN :
0-7803-8752-X
DOI :
10.1109/IITC.2005.1499905
