Title :
Decimal addition and subtraction units using the p-valued decimal signed-digit number representation
Author :
Muranaka, Noriaki ; Imanishi, Shigeru ; Miller, D.M.
Author_Institution :
Dept. of Electron., Kansai Univ., Osaka, Japan
Abstract :
Parallel addition and subtraction of two numbers with signed-digit number representation can be performed in constant time. A signed-digit representation for radix r=10 (SD10R) is presented, and the usefulness of asymmetrical SD10R is considered. The authors propose p(qk. . .q1)-valued SD10Rs in which p is represented as a combination of qk to q1. They also describe a p(q2q1)-valued SD10R addition and subtraction unit in which p is large. Simulation data for typical SD10Rs are compared
Keywords :
adders; digital arithmetic; logic circuits; many-valued logics; SD10R; addition; number representation; signed-digit; signed-digit representation; subtraction; Adders; Circuit noise; Equations;
Conference_Titel :
Multiple-Valued Logic, 1993., Proceedings of The Twenty-Third International Symposium on
Conference_Location :
Sacramento, CA
Print_ISBN :
0-8186-3350-6
DOI :
10.1109/ISMVL.1993.289555
