• DocumentCode
    1838610
  • Title

    Algorithm and implementation of a learning multiple-valued logic network

  • Author

    Cao, Qi-Xin ; Ishizuka, Okihiko ; Tang, Zheng ; Matsumoto, Hiroki

  • Author_Institution
    Fac. of Eng., Miyazaki Univ., Japan
  • fYear
    1993
  • fDate
    24-27 May 1993
  • Firstpage
    202
  • Lastpage
    207
  • Abstract
    A learning technique and implementation for multiple-valued logic (MVL) networks are described. The learning problem is formulated as a minimization of an error function that represents a measure of distortion between actual and desired output. A gradient-based least-square-error minimization algorithm is used to minimize the error function, which in contrast to the backpropagation algorithm, does not involve a sigmoid function and requires only a simple sgn function in the learning rule. The algorithm trains the networks using examples and appears to be available in practice for most multiple-valued problems of interest. Circuit implementations of the learning MVL networks using CMOS current-mode circuits are described
  • Keywords
    learning (artificial intelligence); logic circuits; many-valued logics; minimisation; distortion; error function; gradient-based; learning multiple-valued logic network; learning rule; learning technique; least-square-error minimization; minimization; multiple-valued logic; Arithmetic; Backpropagation algorithms; CMOS logic circuits; Current mode circuits; Distortion measurement; Logic functions; Logic testing; Minimization methods; Neural networks; Piecewise linear techniques;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Multiple-Valued Logic, 1993., Proceedings of The Twenty-Third International Symposium on
  • Conference_Location
    Sacramento, CA
  • Print_ISBN
    0-8186-3350-6
  • Type

    conf

  • DOI
    10.1109/ISMVL.1993.289559
  • Filename
    289559