Title :
Novel CMOS scan design for VLSI testability
Author :
Wu, Huwei ; Zhuang, N. ; Perkowski, M.A.
Author_Institution :
Dept. of Electr. Eng., Portland State Univ., OR
Abstract :
A CMOS scan design that uses a ternary clock signal is presented. The routing of the long mode-control input signal is thus eliminated. Unlike previous efforts to eliminate the mode-control input, no additional MOS transistors are required in this design. Moreover, it has the same CMOS network as the traditional design; only the thresholds of the MOS transistors are varied. Computer simulations with SPICE2G5 show that it can realize the expected logic functions and it has the desirable transfer characteristics
Keywords :
CMOS integrated circuits; VLSI; circuit analysis computing; integrated circuit testing; CMOS scan design; SPICE2G5; VLSI testability; computer simulation; long mode-control input signal; ternary clock signal; thresholds; transfer characteristics; Circuit testing; Clocks; Feeds; Flip-flops; Latches; Logic design; Master-slave; Multiplexing; Signal design; Very large scale integration;
Conference_Titel :
Multiple-Valued Logic, 1993., Proceedings of The Twenty-Third International Symposium on
Conference_Location :
Sacramento, CA
Print_ISBN :
0-8186-3350-6
DOI :
10.1109/ISMVL.1993.289577
