• DocumentCode
    1839102
  • Title

    Development of digital RF memory based target echo simulator for Doppler RADARS

  • Author

    Chakravarti, Madhumita ; Daggula, Rajender

  • fYear
    2009
  • fDate
    14-16 Dec. 2009
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    Radar target echo simulators are needed for calibrating and testing of various Radar systems. A low cost novel implementation of target echo simulator is demonstrated in this paper. Various parameters like target range, range rate, atmospheric attenuation had been simulated using Digital RF Memory technique. The simulated target echo is then sent into the radar signal for test and evaluation. The echo simulator is programmable and can be used for testing of various radar systems.
  • Keywords
    Doppler radar; echo; digital RF memory; doppler radars; radar systems; radar target echo simulators; DDFS Direct Digital Frequency Synthesizer; DRFM Digital RF Memory; FPGA Field Programmable Gate Array; IOB Input Output Block; PDU Programmable Delay Unit; SFDR Spurious Free Dynamic Range;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Applied Electromagnetics Conference (AEMC), 2009
  • Conference_Location
    Kolkata
  • Print_ISBN
    978-1-4244-4818-0
  • Electronic_ISBN
    978-1-4244-4819-7
  • Type

    conf

  • DOI
    10.1109/AEMC.2009.5430576
  • Filename
    5430576
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1839102