Bit-level optimized FIR filter architectures for high-speed decimation applications

Analog-to-digital converters based on sigma-delta modulation have shown promising performance, with steadily increasing bandwidth. However, associated with the increasing bandwidth is an increasing output sample rate, which becomes costly to decimate in the digital domain. Commonly, cascaded integrator comb structures have been used for the first decimation stage, but polyphase decomposed FIR filter architectures have been shown to be more power efficient. In this paper, a bit-level optimization algorithm is introduced, and applied to the direct form and transposed form FIR filter architectures. Mainly, two conclusions can be drawn. The transposed architecture has significantly lower complexity in most circumstances, and the inability to implement an efficient adder prohibits the symmetry of the filter coefficients to be used efficiently for the direct form architecture.