An area-efficient sampling rate converter using negative feedback technique

A new architecture of a sampling rate converter for high oversampling delta-sigma analog-to-digital converters is presented. The proposed system using a negative feedback technique can greatly reduce the hardware, achieving the rate conversion of the large decimation ratio and the sufficient aliasing suppression with linear phase shift characteristic. A design example is given to demonstrate that the sine function. Compared with a conventional cascaded integrator-comb decimation Alter, a 67% area saving is achieved by the proposed converter.