A VLSI architecture using local memory management for large DFT implementation

Author

Bourguet, J.-M. ; Nancy, Th ; Wei, S.J. ; Leroy, J. ; Crappe, R.G.

Author_Institution

Lab. of Microelectron., Fac. Polytech. de Mons, Belgium

fYear

1995

fDate

24-28 Oct 1995

Firstpage

709

Lastpage

711

Abstract

With the progress of VLSI technology, the main performance constraint is not the calculation speed but the access to the external memory. In this paper we introduce an extension of Cooley-Tuckey algorithm (CT) that increases the temporal locality of memory references, enabling efficient use of a small fast on chip memory

Keywords

VLSI; cache storage; digital signal processing chips; discrete Fourier transforms; storage management; Cooley-Tuckey algorithm; VLSI architecture; external memory access; large DFT implementation; local memory management; memory references; performance constraint; temporal locality; Costs; Digital systems; Memory architecture; Memory management; Microelectronics; Multidimensional systems; Read-write memory; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology, 1995 4th International Conference on

Conference_Location

Beijing

Print_ISBN

0-7803-3062-5

Type

conf

DOI

10.1109/ICSICT.1995.503535

Filename

503535

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1839283