Design and performance analysis of HomePNA 2.0 transceiver chip circuit

Author

Kim, Jong Won ; Huh, Jae Doo ; Kim, Dae Young

Author_Institution

Sensor Networking Res. Team, Electron. & Telecommun. Res. Inst., Daejeon

Volume

3

fYear

2006

fDate

20-22 Feb. 2006

Lastpage

1705

Abstract

In this paper, we present the architecture of Home Phoneline Networking Alliance (HomePNA) 2.0 transceiver chip circuit which can establish a home network using existing in-home phone line, and it provides a data rate of 4-32 Mbps. We evaluate the performance of HomePNA 2.0 transceiver chip by running a simulation to study mean squared error (MSE), eye diagram and constellation. By analyzing the results of each simulation, we also analyze the performance of HomePNA 2.0 transceiver chip in a comprehensive manner

Keywords

home automation; mean square error methods; network synthesis; radiofrequency integrated circuits; transceivers; 4 to 32 Mbit/s; Home Phoneline Networking Alliance; HomePNA 2.0; MSE; in-home phone line; transceiver chip circuit; Analytical models; Circuit simulation; Constellation diagram; Frequency; Media Access Protocol; Performance analysis; Physical layer; Quadrature amplitude modulation; Signal analysis; Transceivers; HomePNA; mean squared error; medium access control; physical layer; transceiver;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Communication Technology, 2006. ICACT 2006. The 8th International Conference

Conference_Location

Phoenix Park

Print_ISBN

89-5519-129-4

Type

conf

DOI

10.1109/ICACT.2006.206316

Filename

1625921