DocumentCode :
1839568
Title :
Methodology for yield analysis based on targeted defect impact studies
Author :
Skumanich, Andy ; Ryabova, Elmira
fYear :
2001
fDate :
2001
Firstpage :
283
Lastpage :
286
Abstract :
A methodology is outlined to establish the prioritization of defects under conditions of low sampling statistics based on the deliberate introduction of defects at specific process points. Probe results from electrical test structures are correlated with optical defect inspection data to determine the kill rates of various defects. The methodology generalizes from a standard approach that typically relies on a high statistical sampling plan with significant wafer area coverage. In this case, the probed area coverage is reduced to 1-3% of the wafer surface but still provides defect impact prioritization for targeted defect reduction and optimized inspection strategies
Keywords :
inspection; integrated circuit testing; integrated circuit yield; defect impact prioritization; defect inspection; defect kill rate; electrical test structure; sampling statistics; targeted defect reduction; wafer area coverage; yield analysis; Feedback loop; Inspection; Optical feedback; Optical materials; Personnel; Probes; Sampling methods; Statistical analysis; Statistics; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Semiconductor Manufacturing Symposium, 2001 IEEE International
Conference_Location :
San Jose, CA
Print_ISBN :
0-7803-6731-6
Type :
conf
DOI :
10.1109/ISSM.2001.962968
Filename :
962968
Link To Document :
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