Title :
Design of a multiplier with low power data-compressors
Author_Institution :
Semicond. Design Center, Samsung Electron. Co. Ltd., South Korea
Abstract :
A parallel structured 54×54 bit multiplier with low power data compressors is proposed. Using a tally-function circuit, an optimized low power data compressor is designed. The average power consumption of the proposed data compressor is reduced by about 35%, compared with that of the conventional multiplier; while the propagation delay is nearly same as that of the conventional one
Keywords :
data compression; multiplying circuits; 54 bit; design; low power data compressor; multiplier; parallel structure; power consumption; propagation delay; tally-function circuit; Adders; CMOS process; Circuits; Compressors; Data compression; Delay effects; Design optimization; Energy consumption; Parasitic capacitance; Propagation delay;
Conference_Titel :
Solid-State and Integrated Circuit Technology, 1995 4th International Conference on
Conference_Location :
Beijing
Print_ISBN :
0-7803-3062-5
DOI :
10.1109/ICSICT.1995.503556
