Area oriented pass-transistor logic synthesis using buffer elimination and layout compaction

This paper presents a cell-based AISC design flow where the traditional CMOS cell library is replaced by pass-transistor logic (PTL) cell library. In particular, we develop an automatic PTL logic synthesizer to perform area-oriented synthesis by exploiting the characteristics of the PTL cell circuits. Two methods are used to reduce the area cost. The first method, called buffer elimination, for the pre-layout area minimization is to reduce the redundant inverters in the gate-level netlist during the logic mapping stage and results in an area saving of more than 50%. The second method, called layout compaction, is to reduce the layout area in the physical level by considering the design rules imposed on the PTL cell circuits, and lead to an additional 30% area saving.