Title :
The PowerPC 601 microprocessor
Author_Institution :
IBM Corp., Austin, TX, USA
Abstract :
A highly integrated, single-chip microprocessor is described that combines a powerful reduced instruction set computer (RISC) architecture with a superscalar machine organization and a versatile, high-performance bus interface. The PowerPC 601 microprocessor contains a 32-kbyte cache and is capable of dispatching, executing, and completing up to three instructions per cycle. The bus interface can be configured for a wide range of system bus interfaces, including pipelined, nonpipelined, and split transactions. In addition, the processor is equipped with features suitable for symmetric multiprocessing applications. The result is a cost-effective, general-purpose microprocessor solution that offers very competitive performance.<>
Keywords :
microprocessor chips; reduced instruction set computing; 32-kbyte cache; PowerPC 601 microprocessor; high-performance bus interface; reduced instruction set computer; single-chip microprocessor; split transactions; superscalar machine organization; symmetric multiprocessing applications; Circuit synthesis; Costs; Delay; Hardware; Logic; Microprocessors; Pipelines; Process design; Processor scheduling; Reduced instruction set computing;
Conference_Titel :
Compcon Spring '93, Digest of Papers.
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-8186-3400-6
DOI :
10.1109/CMPCON.1993.289646
