DocumentCode :
1839760
Title :
Multiprocessing aspects of the PowerPC 601
Author :
Allen, M.S. ; Becker, M.C.
Author_Institution :
Motorola Inc., Austin, TX, USA
fYear :
1993
fDate :
22-26 Feb. 1993
Firstpage :
117
Lastpage :
126
Abstract :
The authors describe the multiprocessing capabilities of the PowerPC architecture and the first implementation of that architecture, the 601 microprocessor. The architected multiprocessing (MP) facilities of PowerPC are presented, and the 601 microarchitecture and system interface are discussed in the context of multiprocessing support. It is pointed out that the PowerPC architecture and the 601 seek to advance the state of the art for multiprocessing by providing a building block that addresses full MP functionality and MP performance in a way that has little risk for the system designer and with performance features heretofore unavailable in the microprocessor marketplace.<>
Keywords :
microprocessor chips; multiprocessing systems; PowerPC 601; microarchitecture; microprocessor; multiprocessing aspects; system interface; Bandwidth; Computer architecture; Control systems; File servers; Hardware; Instruction sets; Logic; Microarchitecture; Microprocessors; Multiprocessing systems;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Compcon Spring '93, Digest of Papers.
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-8186-3400-6
Type :
conf
DOI :
10.1109/CMPCON.1993.289647
Filename :
289647
Link To Document :
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