Overview of the START(*T) multithreaded computer

The author provides an overview of the START(*T) computer system being implemented by MIT and Motorola. *T is a scalable computer architecture designed to support a broad variety of parallel programming styles, including those which use multithreading to tolerate the increases in memory latency which occur as the machine size is scaled up. The hardware uses a customized reduced instruction set computer (RISC) microprocessor with a network messaging interface and synchronization unit tightly coupled into the processor architecture. This hardware is coupled with a high-performance network having a fat-tree topology with high cross-section bandwidth. In addition, a HIPPI I/O system provides access to the world of supercomputer-class I/O devices. An innovative software architecture is layered on this hardware to produce a working system which is at its foundation a UNIX-like software environment. The software architecture specifies the structure of parallel programs and the way that they can be controlled and debugged.<>