Fault chip defect characterization for wafer scale integration

Author

Hannaman, D.J. ; Sayah, H.R. ; Allen, R.A. ; Buehler, M.G. ; Yung, Michael

Author_Institution

Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA

fYear

1990

fDate

5-7 March 1990

Firstpage

67

Lastpage

71

Abstract

A fault chip was designed and fabricated on a 2- mu m CMOS wafer-scale integration (WSI) process with greater than 90% wafer coverage. The chip consists of pinhole array capacitors, serpentine resistors, and comb resistors. These structures are tailored to simulate the basic cell in the WSI circuit. Defect cluster analysis, using the negative binomial distribution, indicated that significant clustering occurs for a number of defect types and varies from wafer to wafer.<>

Keywords

CMOS integrated circuits; VLSI; circuit layout; integrated circuit technology; integrated circuit testing; 2 micron; 90% wafer coverage; CMOS WSI process; WSI; comb resistors; defect cluster analysis; defect types; fault defect test structures; negative binomial distribution; pinhole array capacitors; serpentine resistors; wafer scale integration; CMOS technology; Circuit faults; Circuit testing; Laboratories; Propulsion; Redundancy; Resistors; Semiconductor device measurement; Very large scale integration; Wafer scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 1990. ICMTS 1990. Proceedings of the 1990 International Conference on

Conference_Location

San Diego, CA, USA

Type

conf

DOI

10.1109/ICMTS.1990.67882

Filename

67882