DocumentCode
1840092
Title
ESD design challenges in 28nm hybrid FDSOI/Bulk advanced CMOS process
Author
Dray, A. ; Guitard, N. ; Fonteneau, P. ; Golanski, D. ; Fenouillet-Beranger, C. ; Beckrich, H. ; Sithanandam, R. ; Benoist, T. ; Legrand, C.-A. ; Galy, Ph
Author_Institution
STMicroelectron., Crolles, France
fYear
2012
fDate
9-14 Sept. 2012
Firstpage
1
Lastpage
7
Abstract
This paper presents an innovative way to design competitive ESD protection networks in advanced FDSOI CMOS technology thanks to Hybrid Bulk co-integration. An optimal placement of elementary ESD devices is discussed and their ESD performances are compared. The advantage of the co-integration is also demonstrated on an ESD network design development.
Keywords
CMOS integrated circuits; electrostatic discharge; silicon-on-insulator; ESD design; ESD network design development; ESD protection network; Si; elementary ESD device; hybrid FDSOI-bulk advanced CMOS process; hybrid bulk co-integration; size 28 nm; BiCMOS integrated circuits; Capacitance; Clamps; Electrostatic discharges; Logic gates; Performance evaluation; Thyristors;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2012 34th
Conference_Location
Tucson, AZ
ISSN
0739-5159
Print_ISBN
978-1-4673-1467-1
Type
conf
Filename
6333281
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