Title :
Gate stack preparation with high-k materials in a cluster tool
Author :
Gendt, Stefan ; Heyns, Marc ; Conard, Thierry ; Hohira, H. ; Richard, Olivier ; Vandervorst, Wilfried ; Caymax, Matty ; Maes, Jan-Willem ; Tuominen, Marko
Author_Institution :
IMEC, Leuven, Belgium
Abstract :
Oxide layers of metals such as Zr and Al are possible candidates to replace SiO2 as gate dielectric for sub-1 nm EOT (Equivalent Oxide Thickness). We discuss the use of a cluster tool featuring pre-cleaning, surface treatment, metal oxide deposition and electrode deposition modules. Contamination is found to be well within specifications. Throughput is reasonable and we indicate ways how to further improve it. We describe briefly the four modules, and give first process results. An EOT of 0.77 nm measured in a capacitor with a combined Al2O3, and ZrO2 layer is presented. We discuss the importance of a cluster tool for this application based on those process results
Keywords :
CMOS integrated circuits; alumina; chemical vapour deposition; cluster tools; dielectric thin films; integrated circuit manufacture; nitridation; surface contamination; surface treatment; vapour phase epitaxial growth; zinc compounds; 0.77 to 1 nm; ALCVD module; Al2O3; CMOS IC production; CMOS technology scaling; HF vapor module; SiGe; SiGe epitaxial growth; ZrO2; cluster tool; contamination specifications; electrode deposition module; equivalent oxide thickness; gate dielectric; gate stack preparation; high-k materials; manufacturing; metal oxide deposition module; nitride module; oxide layers; poly module; pre-cleaning module; sub-1nm EOT; surface treatment module; throughput improvement; wafer handler platform; CMOS technology; Electrodes; Hafnium; High K dielectric materials; High-K gate dielectrics; Inductors; Surface contamination; Throughput; Tunneling; Zirconium;
Conference_Titel :
Semiconductor Manufacturing Symposium, 2001 IEEE International
Conference_Location :
San Jose, CA
Print_ISBN :
0-7803-6731-6
DOI :
10.1109/ISSM.2001.962998
