Current and future challenges of DRAM metallization

Author

Weber, Detlef ; Thies, Andreas ; Kahler, Uwe ; Lepper, Marco ; Schutz, Ronald

Author_Institution

Memory Products Div., Infineon Technol., Dresden, Germany

fYear

2005

fDate

6-8 June 2005

Firstpage

185

Lastpage

187

Abstract

The challenges and requirements of current and future DRAM interconnect schemes are described. In contrast to most logic metallization development and manufacturing, these requirements include tight pitches in array area, low resistance in the chip periphery, contacts with landing area smaller than the contacts themselves, AlCu fill into high aspect ratio contacts, continued drive toward lower capacitances and, perhaps above all, low cost.

Keywords

DRAM chips; aluminium alloys; capacitance; copper alloys; integrated circuit interconnections; integrated circuit metallisation; AlCu; DRAM interconnect schemes; DRAM metallization; aluminium-copper fill; capacitance; chip periphery; high aspect ratio contacts; logic metallization; low cost; resistance; Contact resistance; Costs; Logic arrays; Logic devices; Manufacturing; Metallization; Parasitic capacitance; Random access memory; Tungsten; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference, 2005. Proceedings of the IEEE 2005 International

Print_ISBN

0-7803-8752-X

Type

conf

DOI

10.1109/IITC.2005.1499974

Filename

1499974

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1840373