Title :
Multiprocessor features of the HP Corporate Business Servers
Author :
Chan, K. ; Alexander, T. ; Hu, C. ; Larson, D. ; Noordeen, N. ; VanAtta, Y. ; Wylegala, T. ; Ziai, S.
Author_Institution :
Hewlett-Packard Co., Palo Alto, CA, USA
Abstract :
The authors describe the multiprocessor features of Hewlett-Packard´s (HP´s) new high-performance Corporate Business Servers. The present implementation uses 60-MHz PA-RISC (reduced instruction set computer) CPUs interconnected with a high-speed processor memory bus to support symmetric eight-way multiprocessing. The focus is on the features and design decisions which allow the system to achieve excellent online transaction processing performance and efficient multiprocessor scaling. The system was designed to provide for scalability of processors, memory, and I/O adapters, and to accommodate multiple generations of processors. The system makes use of fast CPUs with large caches, a high-speed pipelined processor memory bus, duplicate cache tags on the processor modules for fast coherency checking, cache-to-cache transfers for coherency resolution, and highly interleaved large physical memory.<>
Keywords :
multiprocessing systems; performance evaluation; reduced instruction set computing; transaction processing; HP Corporate Business Servers; I/O adapters; cache-to-cache transfers; design decisions; duplicate cache tags; fast coherency checking; high-speed pipelined processor memory bus; highly interleaved large physical memory; multiprocessor features; multiprocessor scaling; online transaction processing performance; reduced instruction set computer; Aggregates; Backplanes; Bandwidth; Circuit synthesis; Companies; Protocols; Reduced instruction set computing; Scalability; Software systems; System buses;
Conference_Titel :
Compcon Spring '93, Digest of Papers.
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-8186-3400-6
DOI :
10.1109/CMPCON.1993.289690