DocumentCode :
1840509
Title :
Temporally learning floating-gate VLSI synapses
Author :
Liu, Shih Chii ; Mockel, Rico
Author_Institution :
Inst. of Neuroinformatics, Univ. of Zurich & ETH Zurich, Zurich
fYear :
2008
fDate :
18-21 May 2008
Firstpage :
2154
Lastpage :
2157
Abstract :
We present a floating-gate synaptic circuit that updates its weight according to the spike-timing-dependent plasticity (STDP) rule. The weight (or floating-gate voltage) is updated only if the time difference between the pre- and post-synaptic spikes falls within a learning window. The update is implemented through tunneling and injection mechanisms which can be tuned for very long time constants up to seconds. The novelty of this circuit is that the tunneling and injection mechanisms are turned on only when the correlation of the pre and postsynaptic activity is significant. The additional benefit of this non-volatile technology is that synaptic weights can be stored locally on chip. We present experimental results that show the learning and normalization effects from the fabricated circuits.
Keywords :
VLSI; floating point arithmetic; logic design; VLSI synapses; floating-gate synaptic circuit; floating-gate voltage; injection mechanism; learning window; spike-timing-dependent plasticity; synaptic spikes; tunneling mechanism; Analog memory; Leakage current; Learning systems; Nonvolatile memory; Pulse circuits; Pulse generation; Tunneling; Unsupervised learning; Very large scale integration; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
978-1-4244-1683-7
Electronic_ISBN :
978-1-4244-1684-4
Type :
conf
DOI :
10.1109/ISCAS.2008.4541877
Filename :
4541877
Link To Document :
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