Title :
Analysis of ESD fails in a 45 nm mixed signal SoC
Author_Institution :
NXP Semicond., Nijmegen, Netherlands
Abstract :
The analysis of ESD qualification fails for a large IC is presented. With a careful procedure all fails are explained. Several failures are related to stress accumulation. This is unlikely to occur in assembly lines. ESD qualification procedures should take this into account. This saves test, analysis and redesign costs.
Keywords :
assembling; electrostatic discharge; failure analysis; integrated circuit reliability; mixed analogue-digital integrated circuits; stress analysis; system-on-chip; ESD failure analysis; assembly lines; large IC; mixed signal SoC; size 45 nm; stress accumulation; Clamps; Electrostatic discharges; Force; Logic gates; Probes; Qualifications; Stress;
Conference_Titel :
Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2012 34th
Conference_Location :
Tucson, AZ
Print_ISBN :
978-1-4673-1467-1
