Title :
Latch-up characterization and checking of a 55 nm CMOS mixed voltage design
Author :
Oberoi, Anirudh ; Khazhinsky, Michael ; Smith, Jeremy ; Moore, Bill
Author_Institution :
Silicon Labs., Singapore, Singapore
Abstract :
Mixed Voltage Design has become predominant in the semiconductor industry due to the integration of high voltage and low voltage circuits in the pad ring. Latch-up characterization and analysis of a 55 nm CMOS technology has been done to determine the effects of various protection strategies on the trigger and holding parameters of SCRs to develop a design rule checker.
Keywords :
CMOS integrated circuits; integrated circuit design; semiconductor industry; thyristors; CMOS mixed voltage design; CMOS technology; SCR; design rule checker; high voltage circuits; latch-up characterization; low voltage circuits; pad ring; protection strategy; semiconductor industry; size 55 nm; Couplings; Layout; MOS devices; Resistance; Structural rings; Switches; Thyristors;
Conference_Titel :
Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2012 34th
Conference_Location :
Tucson, AZ
Print_ISBN :
978-1-4673-1467-1
