Title :
Linewidth and step resistance distribution measurements using an addressable array
Author :
Sayah, Hoshyar ; Buehler, Martin
Author_Institution :
Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA
Abstract :
A test structure is introduced which uses column and row decoding to measure variations in linewidths and step-coverage resistances for a large sample size within a small area. A model was developed to explain the results. The structure is intended to qualify manufacturing lines used in producing ASICs. Therefore, it is designed using parameterized features to accommodate geometrical design rules. The structure was fabricated using a 2- mu m CMOS process and tested with a parametric test system. Test results show that linewidth and step resistance control is best for polysilicon layers and worst for secondary metallic layers.<>
Keywords :
CMOS integrated circuits; application specific integrated circuits; integrated circuit manufacture; integrated circuit technology; integrated circuit testing; quality control; 2 micron; CMOS process; addressable array; column and row decoding; geometrical design rules; large sample size; linewidth distribution measurement; parameterized features; parametric test system; polycrystalline Si layers; polysilicon layers; process control chips; producing ASICs; qualify manufacturing lines; secondary metallic layers; step resistance control; step resistance distribution measurements; step-coverage resistances; test structure; variations in linewidths; Area measurement; Bridge circuits; Circuit testing; Electrical resistance measurement; Probes; Propulsion; Resistors; System testing; Topology; Wires;
Conference_Titel :
Microelectronic Test Structures, 1990. ICMTS 1990. Proceedings of the 1990 International Conference on
Conference_Location :
San Diego, CA, USA
DOI :
10.1109/ICMTS.1990.67885
