Title :
A quantitative approach to benchmarking programmable logic architectures
Author_Institution :
Intel Corp., Folsom, CA, USA
Abstract :
Describes a set of metrics based on analytical methods which evaluate the efficiency of programmable logic architectures, whether programmable logic device (PLD), programmable logic array (PLA), field-programmable gate array (FPGA), or complex channeled PLD (CPLD). The metrics are easily derived and form an equable measure of architectural efficiency across any device. Further, the metrics provide a pragmatic approach to device selection by quantifying the demands of a circuit, and comparing this against the availability of resources within a programmable architecture. In addition, the author provides a tutorial on the use of the metrics while focusing on a quantitative approach to benchmarking.<>
Keywords :
computer architecture; logic arrays; performance evaluation; FPGA; analytical methods; architectural efficiency; benchmarking; circuit demands; complex channeled PLD; device selection; field-programmable gate array; metrics; pragmatic approach; programmable logic architectures; programmable logic array; programmable logic device; quantitative approach; resource availability; Circuits; Cities and towns; Field programmable gate arrays; Logic devices; Measurement standards; Network topology; Pins; Programmable logic arrays; Programmable logic devices; Roads;
Conference_Titel :
Compcon Spring '93, Digest of Papers.
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-8186-3400-6
DOI :
10.1109/CMPCON.1993.289705
