Title :
Concurrent fault tolerant control of semiconductor measurement and testing
Author :
Blunn, Robert G. ; Dorough, Michael J. ; Velichko, Sergey A.
Author_Institution :
Micron Technol. Inc., Boise, ID, USA
Abstract :
Fault tolerant modeling constraints are presented to reduce wafer test times attributed to sequential semiconductor measurement and testing (SMT) and to avoid product damage and deviation in quality during testing. The concept is expressed using the Unified Modeling Language statecharts and is further reinforced with a mathematical finite-state machine. By adhering to constraints, translation of this object-oriented model to the solution space has been successfully applied to a parametric in-line testing system (PITS) resulting in significant reduction of test time. PITS statistical data is used to support our models by comparing previous sequential implementation to our new concurrent approach
Keywords :
fault tolerance; finite state machines; integrated circuit measurement; integrated circuit testing; object-oriented methods; process control; production engineering computing; production testing; quality control; specification languages; SMT; concurrent fault tolerant control; finite-state machine; object-oriented model; parametric in-line testing system; product damage; quality; sequential semiconductor measurement and testing; solution space; test time; unified modeling language statecharts; wafer test times; Data analysis; Fault tolerance; Object oriented modeling; Semiconductor device manufacture; Semiconductor device modeling; Semiconductor device testing; Sequential analysis; Surface-mount technology; System testing; Unified modeling language;
Conference_Titel :
Semiconductor Manufacturing Symposium, 2001 IEEE International
Conference_Location :
San Jose, CA
Print_ISBN :
0-7803-6731-6
DOI :
10.1109/ISSM.2001.963014