DocumentCode :
1840959
Title :
Hardware support for high performance, intrusion- and fault-tolerant systems
Author :
Saggese, G.P. ; Basile, C. ; Romano, L. ; Kalbarczyk, Z. ; Iyer, R.K.
Author_Institution :
Illinois Univ., Urbana, IL, USA
fYear :
2004
fDate :
18-20 Oct. 2004
Firstpage :
195
Lastpage :
204
Abstract :
The paper proposes a combined hardware/software approach for realizing high performance, intrusion- and fault-tolerant services. The approach is demonstrated for (yet not limited to) an attribute authority server, which provides a compelling application due to its stringent performance and security requirements. The key element of the proposed architecture is an FPGA-based, parallel crypto-engine providing (1) optimally dimensioned RSA Processors for efficient execution of computationally intensive RSA signatures and (2) a KeyStore facility used as tamper-resistant storage for preserving secret keys. To achieve linear speed-up (with the number of RSA Processors) and deadlock-free execution in spite of resource-sharing and scheduling/synchronization issues, we have resorted to a number of performance enhancing techniques (e.g., use of different clock domains, optimal balance between internal and external parallelism) and have formally modeled and mechanically proved our crypto-engine with the Spin model checker. At the software level, the architecture combines active replication and threshold cryptography, but in contrast with previous work, the code of our replicas is multithreaded so it can efficiently use an attached parallel crypto-engine to compute an attribute authority partial signature (as required by threshold cryptography). Resulting replicated systems that exhibit nondeterministic behavior, which cannot be handled with conventional replication approaches. Our architecture is based on a preemptive deterministic scheduling algorithm to govern scheduling of replica threads and guarantee strong replica consistency.
Keywords :
authorisation; cryptography; digital signatures; fault tolerant computing; hardware-software codesign; program verification; scheduling; software architecture; FPGA-based parallel crypto-engine; KeyStore facility; Spin model checker; active replication; attached parallel crypto-engine; attribute authority partial signature; attribute authority server; computationally intensive RSA signature; formal modeling; hardware-software approach; high performance fault-tolerant service; high performance fault-tolerant system; high performance intrusion-tolerant service; high performance intrusion-tolerant system; optimally dimensioned RSA Processor; preemptive deterministic scheduling; replica consistency; replica threads; replicated system; security requirement; tamper-resistant storage; threshold cryptography; Application software; Computer architecture; Concurrent computing; Cryptography; Fault tolerance; Fault tolerant systems; Hardware; Processor scheduling; Software performance; System recovery;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Reliable Distributed Systems, 2004. Proceedings of the 23rd IEEE International Symposium on
ISSN :
1060-9857
Print_ISBN :
0-7695-2239-4
Type :
conf
DOI :
10.1109/RELDIS.2004.1353020
Filename :
1353020
Link To Document :
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