DocumentCode :
1841027
Title :
Pathlengths of SPEC benchmarks for PA-RISC, MIPS, and SPARC
Author :
McMahan, L. ; Lee, R.
Author_Institution :
Hewlett Packard Co., Cupertino, CA, USA
fYear :
1993
fDate :
22-26 Feb. 1993
Firstpage :
481
Lastpage :
490
Abstract :
The total instruction pathlength and instruction frequency counts are measured for the SPEC89 benchmark programs on the PA-RISC architecture and compared with previously published information for the MIPS and SPARC architectures. The PA-RISC architecture typically requires significantly fewer instructions than the other two architectures for the same benchmark. The differences in counts for instruction subclasses are compared and used to estimate the actual impact of some PA-RISC architectural features designed for pathlength reduction. The total geometric mean of the ratio of pathlengths showed that both MIPS and SPARC executed 33% more instructions than PA-RISC. Since these programs are large and different in nature, this may be considered a significant empirical measure of the effectiveness of the PA-RISC pathlength reduction features in both its instruction-set architecture and its compilers.<>
Keywords :
computer architecture; multiprocessing systems; performance evaluation; program compilers; reduced instruction set computing; workstations; MIPS architecture; PA-RISC architecture; SPARC architecture; SPEC89 benchmark programs; compilers; instruction frequency counts; instruction subclasses; instruction-set architecture; pathlength reduction; total instruction pathlength; Computer aided instruction; Computer architecture; Delay; Frequency measurement; Hardware; Home computing; Indexing; Pipelines; Reduced instruction set computing; Registers;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Compcon Spring '93, Digest of Papers.
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-8186-3400-6
Type :
conf
DOI :
10.1109/CMPCON.1993.289718
Filename :
289718
Link To Document :
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