Challenges and opportunities in nano-scale VLSI design

Moore´s law continues to drive the scaling of CMOS technology (Moore, 1965), The feature size of the transistor now has been shrunk well into nano-scale region (Bohr, 2002). A large single VLSI chip can contain over one billion transistors. The ever-increasing level of integration has enabled higher performance and richer feature sets on a single chip. This has led to the explosive growth of microelectronics industry over last decades. But as the geometry of the transistor is getting smaller and the number of transistors on a single chip grows exponentially, the power management for a state-of-the-art VLSI design has become increasingly important. To maintain the performance trend of the VLSI system as the technology scaling continues, many advanced design techniques, especially in power management, have to be employed in order to achieve a balanced design to meet platform and end-user needs.