DocumentCode :
1841073
Title :
Using behavioural synthesis for hardware generation of a contour-based image segmentation algorithm
Author :
Dossis, Michael ; Amanatidis, Dimitrios ; Androulidakis, Iosif
Author_Institution :
Dept. of Inf. Eng., Technol. Educ. Inst. of Western Macedonia, Kastoria, Greece
fYear :
2015
fDate :
7-9 July 2015
Firstpage :
72
Lastpage :
76
Abstract :
In this contribution, the use of Behavioural Synthesis for hardware generation of a contour-based image segmentation method, is presented. The segmentation method examined is a well-known, state-of-the-art, robust, efficient and fast-converging one, that considers functionals depending on the curve geometry and image properties in a level-set framework. A cost function is built and sought to be minimized, formulated as a weighted sum of three integral measures; a robust alignment term that leads the evolving surface to the edges of the desired object, a minimal variance term that measures the homogeneity inside and outside the object, and a geodesic active surface term that is used mainly for regularization. The algorithm is initially implemented in MatLab and ADA and subsequently, it is ported to our Behavioural Synthesis tool, the CCC HLS framework, which is capable of delivering correct-by-construction RTL VHDL implementations of computation-intensive applications. This way, behavioural ADA specifications are transformed into RTL micro-architectures which then can be easily implemented by commercial RTL synthesizers.
Keywords :
hardware description languages; image segmentation; mathematics computing; CCC HLS framework; MatLab; RTL micro-architectures; RTL synthesizers; behavioural ADA specifications; behavioural synthesis tool; contour-based image segmentation algorithm; contour-based image segmentation method; correct-by-construction RTL VHDL implementations; curve geometry; geodesic active surface term; hardware generation; Conferences; Decision support systems; Hardware; Image segmentation; Contour Segmentation; Custom Coprocessors Compilation; FPGA Implementation; High Level Synthesis;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Information and Digital Technologies (IDT), 2015 International Conference on
Conference_Location :
Zilina
Type :
conf
DOI :
10.1109/DT.2015.7222953
Filename :
7222953
Link To Document :
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