Sources of error in electrical measurements of dimensional offset and sheet resistance in the near- and sub-micron region

Author

Trager, J.

Author_Institution

Siemens AG, Munich, West Germany

fYear

1990

fDate

5-7 March 1990

Firstpage

99

Lastpage

104

Abstract

The accuracy of the measurements of the sheet resistance and dimensional offsets for several conducting layers is investigated using various test structures with design widths ranging from 0.6 mu m to 32 mu m. Width-independence as well as electric field-dependence of the sheet resistance is found to be a main source of error. Different topography beneath resistor stripes and nonisotropic processing in the submicron region further affect the measurement results.<>

Keywords

VLSI; integrated circuit technology; integrated circuit testing; measurement errors; 0.6 to 32 micron; ULSI; design widths; electric field-dependence; electrical measurements of dimensional offset; measurement errors; measurement results; nonisotropic processing; several conducting layers; sheet resistance measurement; source of error; submicron region; test structures; topography effects; width independence; Bridge circuits; Electric resistance; Electric variables measurement; Electrical resistance measurement; Geometry; Logic testing; Measurement errors; Resistors; Surfaces; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 1990. ICMTS 1990. Proceedings of the 1990 International Conference on

Conference_Location

San Diego, CA, USA

Type

conf

DOI

10.1109/ICMTS.1990.67887

Filename

67887