Application specific eFPGAs for SoC platforms

With the continuous progress of CMOS technology the integration of the complete functionality of complex systems becomes feasible on a single die of silicon. Such systems-on-chip (SoC) in future will feature a huge computational power by operating billions of transistors at GHz-clock frequencies. But aside of the well known advantages of systems-on-chip their exploding gate count complexity as well as the physical complexity of future deepsub-micron technologies are facing SoC designers by serious issues. In order to overcome the inevitable problems due to exploding NRE (especially mask) costs the concept of SoC platforms, suited to match the requirements of different customers and applications in a specific domain is applied, allowing to share NRE costs among a high volume of fabricated devices. This platform approach as well as other aspects like the ever-decreasing time-to-market window, need for functionality updates etc. require a high degree of flexibility to be provided on future SoCs. The extensive use of SW-programmable kernels on SoCs offers the highest available flexibility but, although their performance continuously increases, suffers from a too small computational performance for many applications and even more severe is paid for by an unacceptable power penalty. High performance blocks dedicated to standard functionalities (e.g. correlation, filtering, error decoding etc. in frequently used DSP processing) feature orders of magnitude better power and area efficiency but no flexibility at all. An additional implementation alternative attaining more and more attention is the use of reconfigurable embedded FPGA (eFPGA) blocks which allow an attractive compromise between flexibility and efficiency. Especially such eFPGAs seem to be ideally suited as co-processor blocks for efficient acceleration of challenging arithmetic tasks on SW-programmable kernels. The application domain for those reconfigurable accelerators on a SoC platform is quite well defined and therefore they can be tuned to this specific domain, trading flexibility for even better efficiency. As for conventional FPGA devices it is well known, that the communication and reconfiguration overhead contributes with up to 90% to the total power dissipation and silicon area main attention ha- s to be spent on the optimization of communication and reconfiguration resources. Optimization strategies as well as the feasible optimization potential of application specific eFPGAs are presented.