DocumentCode
1841328
Title
Mixed-mode simulations for power-on ESD analysis
Author
Scholz, M. ; Shibkov, A. ; Chen, S.-H. ; Linten, D. ; Thijs, S. ; Sawada, M. ; Vandersteen, G. ; Groeseneken, G.
Author_Institution
Dept. ELEC, Vrije Univ. Brussels, Brussels, Belgium
fYear
2012
fDate
9-14 Sept. 2012
Firstpage
1
Lastpage
9
Abstract
The transient behavior of an on-chip ESD protection device and off-chip components under systemlevel ESD stress is analyzed with mixed-mode simulations. A detailed transient analysis is required to prevent thermal failure when no supply voltage is applied and to prevent latchup when the supply voltage is applied.
Keywords
electrostatic discharge; failure analysis; stress analysis; transient analysis; mixed-mode simulations; off-chip components; on-chip ESD protection device; power-on ESD analysis; system level ESD stress; thermal failure; transient analysis; transient behavior; Capacitors; Electrostatic discharges; Hidden Markov models; Integrated circuit modeling; Stress; Thyristors; Voltage measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2012 34th
Conference_Location
Tucson, AZ
ISSN
0739-5159
Print_ISBN
978-1-4673-1467-1
Type
conf
Filename
6333333
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