An integrated four-antenna 802.11a receiver in 0.25 µm SiGe BiCMOS with spatial weighting

This article presents an integrated receiver (RX) for antenna combining in the radio-frequency (RF) front-end for 802.11a designed in 0.25μm SiGe BiCMOS. The four-element array includes four low noise amplifiers (LNAs), vector modulators (VMs), and a signal combiner. These circuits can weight the incoming C-band (5.6GHz) signals in their I- and Q-components with an 8-bit resolution before superposition and downcoversion. The zero-IF architecture integrates a complete RX including an 8^th order switched-capacitor (SC) filter for channel selection and an automatic gain control (AGC). Together with digital control logic the integrated circuit (IC) has a power consumption of 350mW and an area of 7.5mm².