DocumentCode
1841349
Title
IEC system level ESD challenges and effective protection strategy for USB2 interface
Author
Bertonnaud, Stéphane ; Duvvury, Charvaka ; Jahanzeb, Agha
Author_Institution
Texas Instrum., Villeneuve-Loubet, France
fYear
2012
fDate
9-14 Sept. 2012
Firstpage
1
Lastpage
8
Abstract
We report here a successful OMAP™ system design strategy where TLP information for both the external TVS and the IC pin were combined in an overall simulation procedure that includes the filtering response through the board components. The examples presented here specifically demonstrate the design strategy for a USB2 interface.
Keywords
IEC standards; circuit CAD; electrostatic discharge; peripheral interfaces; printed circuit design; voltage regulators; IC pin; IEC system level ESD challenge; OMAP system design strategy; TLP information; USB2 interface; design strategy; effective protection strategy; external TVS; filtering response; transient voltage suppressor; Electrostatic discharges; IEC; IEC standards; Impedance; Integrated circuit modeling; Universal Serial Bus;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2012 34th
Conference_Location
Tucson, AZ
ISSN
0739-5159
Print_ISBN
978-1-4673-1467-1
Type
conf
Filename
6333334
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