Title :
On-chip quasi-static floating-gate capacitance measurement method
Author_Institution :
Philips Res. Lab., Eindhoven, Netherlands
Abstract :
An accurate interconnect capacitance parameter measurement technique is described. The technique is based on measurement of a capacitively divided DC voltage by means of a source follower stage integrated in the test structure. Determining of dielectric thickness as well as interconnect capacitance parameters using this technique in combination with special test patterns is described. The method shows good agreement with two-dimensional computer simulations. The technique is proven to be practical, reliable, and suited for use with manual and automatic parametric test equipment.<>
Keywords :
CMOS integrated circuits; MOS integrated circuits; capacitance measurement; integrated circuit technology; integrated circuit testing; metallisation; CMOS; MOS ICs; capacitively divided DC voltage; dielectric thickness; interconnect capacitance parameter measurement technique; interconnect capacitance parameters; on-chip capacitance measurement; quasistatic floating-gate capacitance measurement method; source follower stage; test patterns; test structure; two-dimensional computer simulations; Capacitance measurement; Capacitors; Circuit testing; Computer simulation; Integrated circuit interconnections; MOSFET circuits; Measurement techniques; System testing; Test equipment; Voltage;
Conference_Titel :
Microelectronic Test Structures, 1990. ICMTS 1990. Proceedings of the 1990 International Conference on
Conference_Location :
San Diego, CA, USA
DOI :
10.1109/ICMTS.1990.67889
