Title :
New architectures for reduced-state sequence detection with local feedback
Author :
Haratsch, Erich F.
Author_Institution :
Read Channel SoC Archit., ACERB Syst., Allentown, PA, USA
Abstract :
Architectures for reduced-state sequence detection (RSSD) with local feedback are presented that reduce the critical path to an add-compare and select operation independent from the channel memory and allow for data rates that are similar to those achieved by Viterbi detectors without local feedback.
Keywords :
Viterbi detection; channel estimation; maximum likelihood sequence estimation; state feedback; Viterbi detectors; add-compare operation; channel memory; local feedback; reduced-state sequence detection; select operation; Delay estimation; Detectors; Erbium; Error analysis; Feedback; Hardware; Intersymbol interference; Maximum likelihood detection; Maximum likelihood estimation; Viterbi algorithm;
Conference_Titel :
VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT). 2005 IEEE VLSI-TSA International Symposium on
Print_ISBN :
0-7803-9060-1
DOI :
10.1109/VDAT.2005.1500016
