Reconfigurable architectures for network processing

Author

Sezer, Sakir ; McLoone, Maire ; McCanny, John

Author_Institution

Inst. of Electron., Commun. & Inf. Technol., Queen´´s Univ., Belfast, Ireland

fYear

2005

fDate

27-29 April 2005

Firstpage

75

Lastpage

83

Abstract

An overview of research on reconfigurable architectures for network processing applications within the Institute of Electronics, Communications and Information Technology (ECIT) is presented. Three key network processing topics, namely node throughput, Quality of service (QoS) and security are examined where custom reconfigurability allows network nodes to adapt to fluctuating network traffic and customer demands. Various architectural possibilities have been investigated in order to explore the options and tradeoffs available when using reconfigurability for packet/frame processing, packet-scheduling and data encryption/decryption. This research has shown there is no common approach that can be applied. Rather the methodologies used and the cost-benefits for incorporation of reconfigurability depend on each of the functions considered, for example being well suited to encryption/decryption but not packet/frame processing.

Keywords

field programmable gate arrays; network computers; quality of service; reconfigurable architectures; telecommunication security; telecommunication traffic; data encryption/decryption; network processing; network security; network traffic; node throughput; packet scheduling; packet/frame processing; quality of service; reconfigurable architectures; Cryptography; Data security; Energy consumption; Quality of service; Reconfigurable architectures; Reconfigurable logic; Silicon; Telecommunication traffic; Throughput; Web and internet services;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT). 2005 IEEE VLSI-TSA International Symposium on

Print_ISBN

0-7803-9060-1

Type

conf

DOI

10.1109/VDAT.2005.1500024

Filename

1500024